###########################################################################
		UP-APL01 (UP^2)
###########################################################################
Microcode:
| Stepping | Version           |
| -------- | ---------------   |
| SOC A    | N/A               |
| SOC B    | M03506C9_00000028 |
---------------------------------------------------------------------------
Note:

###########################################################################
===========================================================================
BIOS Name:	[UPA1AM21.bin]	 	(based on [UPA1AM20])
Checksum:	[16]MB:[1078]h
Sign-on Message:
		UP-APL01 R2.1 (UPA1AM21)(09/01/2017)

Change:
	Emutex Request : [LPSS I2C #2 Speed] default as [Standard Mode]
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM20.bin]	 	(based on [UPA1AM19])
Checksum:	[16]MB:[1CCA]h
Sign-on Message:
		UP-APL01 R2.0 (UPA1AM20)(08/11/2017)

Change:
	FOR Win10 IoT Core : Support Secure Boot and Disabled as default.
	Fixed : Custom SMBIOS Information will be gone after CMOS Battery lossed
	Fixed : Default Administrator Password will be gone after BIOS Restore Default
	Emutex Request : USB OTG Enabled as Default, and Override Related Register Settings
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM191.bin]	 	(based on [UPA1AM19])
Checksum:	[16]MB:[9B56]h
Sign-on Message:
		UP-APL01 R1.9.1 (UPA1AM19)(07/27/2017)

Change:
	Supported fTPM - Intel PTT

Note: Only for AAEON Internal
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM19.bin]	 	(based on [UPA1AM18])
Checksum:	[16]MB:[3B2A]h
Sign-on Message:
		UP-APL01 R1.9 (UPA1AM19)(07/05/2017)

Change:
	Custom Request : Dynamic Hide a virtual Emutex's ASL Device under Windows, depend on "OS Selection" under Setup Menu
	Fixed : CPU Frequency Incorrect when EIST Disabled
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM18.bin]	 	(based on [UPA1AM17])
Checksum:	[16]MB:[7E78]h
Sign-on Message:
		UP-APL01 R1.8 (UPA1AM18)(06/23/2017)

Change:
	Fixed : Incorrect EN_I2C0 / EN_I2C1 command setting
	Emutex's Request : According to I2C Function Enabled/Disabled, corresponding pins should be Hi-Z
	Support MIPI CSI Camera : OV2740 & OV8856

Camera Support Requirement:
1. Windows 10 RS1
2. Driver Install manully
3. BIOS Setting Change (Administrator Mode)
	CRB Setup -> CRB Chipset -> Uncore Configuration -> IPU Enabled/Disabled : Enabled
	CRB Setup -> CRB Chipset -> Uncore Configuration -> SA IPU ACPI Mode : IGFX Child
	Boot -> OS Selection : Windows

	Only support one kind of camera at the same time
		OV8856 : CRB Setup -> CRB Chipset -> Uncore Configuration -> Rear Camera : IMX135
		OV2740 : CRB Setup -> CRB Chipset -> Uncore Configuration -> Front Camera : OV2740
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM17.bin]	 	(based on [UPA1AM16])
Checksum:	[16]MB:[B73D]h
Sign-on Message:
		UP-APL01 R1.7 (UPA1AM17)(06/14/2017)

Change:
	Emutex's Request : Re-arrange BIOS Setup Menu and BIOS Default Modification
	Emutex's Request : aDSP pubkey only supported cAvsImage1Manifest
	Fixed : Wrong Setup String of Memory Type
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM16.bin]	 	(based on [UPA1AM15])
Checksum:	[16]MB:[DFD3]h
Sign-on Message:
		UP-APL01 R1.6 (UPA1AM16)(06/07/2017)
Change:
	Emutex's Request : USB Device as the 1st boot priority boot device.
	Emutex's Request : All GPIOs as GPIO Drive Mode even it's multi-function pin, and default as MultiFunctions
	Emutex's Request : Built in a custom aDSP public key
	Emutex's Request : Re-arrange BIOS Setup Menu
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM15.bin]	 	(based on [UPA1AM14])
Checksum:	[16]MB:[133F]h
Sign-on Message:
		UP-APL01 R1.5 (UPA1AM15)(05/26/2017)

Change:
	Emutex's Request : Support FPGA initialization during BIOS POST
	Emutex's Request : Fixed GPIO Interrupt Issue
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM14.bin]	 	(based on [UPA1AM13])
Checksum:	[16]MB:[76B9]h
Sign-on Message:
		UP-APL01 R1.4 (UPA1AM14)(05/09/2017)

Change:		
	Emutex's Request : All GPIO Input Pins as "GPIO Driver Mode"
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM13.bin]	 	(based on [UPA1AM12])
Checksum:	[16]MB:[1DE1]h
Sign-on Message:
		UP-APL01 R1.3 (UPA1AM13)(04/24/2017)

Change:		
	Customer's Request (Emutex) : "Console Redirection" : Enabled
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM12.bin]	 	(based on [UPA1AM11])
Checksum:	[16]MB:[61FF]h
Sign-on Message:
		UP-APL01 R1.2 (UPA1AM12)(04/24/2017)

Change:		
	Customer's Request (Emutex) : "VT-d" : Enabled
	Customer's Request (Emutex) : "OS Selection" : Intel Linux
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM11.bin]	 	(based on [UPA1AM10])
Checksum:	[16]MB:[1968]h
Sign-on Message:
		UP-APL01 R1.1 (UPA1AM11)(04/21/2017)

Change:		
	Customer's Request (Emutex) : Emutex released a new ACPI table for bug fixed
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM10.bin]	 	(based on [UPA1AM09])
Checksum:	[16]MB:[4F7D]h
Sign-on Message:
		UP-APL01 R1.0 (UPA1AM10)(04/20/2017)

Change:		
	Customer's Request (Emutex) : Supported BIOS Default Password
	Customer's Request (Emutex) : Re-arrange BIOS Setup Menu
	Customer's Request (Emutex) : Built in a ACPI Table for HAT Function
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM09.bin]	 	(based on [UPA1AM08])
Checksum:	[16]MB:[95B8]h
Sign-on Message:
		UP-APL01 R0.9 (UPA1AM09)(04/17/2017)

Change:		
	Customer's Request (Emutex) : SMBIOS TYPE 2 - BASE BOARD "BASE_BOARD_VERSION" as V0.3
	Customer's Request (Emutex) : Expand Main BIOS Size for reserved.
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM08.bin]	 	(based on [UPA1AM07])
Checksum:	[16]MB:[880F]h
Sign-on Message:
		UP-APL01 R0.8 (UPA1AM08)(04/12/2017)
Change:		
	FOR UP^2, Support Setup Items to Control HAT 40 Pins.
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM07.bin]	 	(based on [UPA1AM06])
Checksum:	[16]MB:[668F]h
Sign-on Message:
		UP-APL01 R0.7 (UPA1AM07)(03/22/2017)
Change:		
	H/W Design: FOR UP-APL01, FAN from PWM2 only supported On or Off
	H/W Design Changed: Support PCIe / mSATA Switch by GPIO Pin
	PM Product Spec. Requirement: FOR UP-APL01, Support Power Button Notify from Wake State
	PM Product Spec. Requirement: FOR UP-APL01, Support USB wake from S3 & S4.
	Upgrade to the latest AAEON CRB Code
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM06.bin]	 	(based on [UPA1AM05])
Checksum:	[16]MB:[5688]h
Sign-on Message:
		UP-APL01 R0.6 (UPA1AM06)(02/21/2017)

Change:		
	Support Uefi PXE boot (Network Stack)
	Support USB ports ejectable feature
	Support Console Redirection feature (HSUART0 only)
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM05.bin]	 	(based on [UPA1AM04])
Checksum:	[16]MB:[E329]h
Sign-on Message:
		UP-APL01 R0.5 (UPA1AM05)(02/10/2017)

Change:		
	FOR H/W A0.3 design changed, re-define SoC GPIO multifunction pins
	FOR FAN default enabled, PWM0 / PWM1 / PWM2 / PWM3 default as GPO High
	"GPIO_37 PWM3" was not floating anymore
	Support CPU DTS temperature
	Arrange BIOS setup
	Fixed: There's a yellow mark under windows(SD Controller)
	H/W A0.3 Changed, DDI0 changed from HDMI to DP
	Built in LPSS Device ASL code
	Only support 1 LPSS UART
	Remove unnecessary ASL devices
	Core Base Upgrade
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM04.bin]	 	(based on [UPA1AM03])
Checksum:	[16]MB:[8AE3]h
Sign-on Message:
		UP-APL01 R0.4 (UPA1AM04)(01/03/2017)

Change:		
	Fine-tuned, Integrated Graphics Power will not be dropped when running Intel TAT Gfx workload
	Adjust SATA Port 0 TX Voltage Swing according to SI's test result.
	Upgrade to the latest AAEON CRB Code
	
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM03.bin]	 	(based on [UPA1AM02])
Checksum:	[16]MB:[BE6B]h
Sign-on Message:
		UP-APL01 R0.3 (UPA1AM03)(12/08/2016)

Changes:
	FOR Apollolake Platform, support GPIO Power Button SCI
	FOR UP-APL01, CPU Frequency Should be Capable to Reach to the Maximum
	Correct SMBIOS Data
	Support OnBoard Flash BIOS under EFI Shell
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM02.bin]	 	(based on [UPA1AM01])
Checksum:	[16]MB:[B613]h
Sign-on Message:
		R0.2 (UPA1AM02)(12/02/2016)

Changes:
	BIOS Default Modification. Cont.
	BIOS Default Modification
	PCIe Ports CLKREQs Routing
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM01.bin]	 	(based on [UPA1AM00])
Checksum:	[16]MB:[9F52]h
Sign-on Message:
		R0.1 (UPA1AM01)(11/29/2016)

Changes:
	PCIe Ports CLKREQs Routing
	FOR UP-APL01, VBIOS Porting in Project Level
	H/W Design Changed from 8MB to 16MB
	FOR UP-APL01, SoC GPIO MultiFunction Pins Porting
	TXE Configuration
===========================================================================
===========================================================================
BIOS Name:	[UPA1AM00.bin]	 	(based on [1ATJS024_M0B])
Checksum:	[8]MB:[D0C2]h
Sign-on Message:
		R0.0 (UPA1AM00)(11/24/2016)

Changes:
	Support Memory Down on UP-APL01, cont. (for UP-APL01 4GB memory down, 1GB x 4)
	FOR UP-APL01, support more than 1 memory down configurations
	Migrate SoC GPIO Pins Configurations to Project Level
	Power Solution : PMIC for UP-APL01
	Override BOARDID for UP-APL01, and FLASH SIZE as 8MB temporarily
	Support Memory Down on UP-APL01, override SMIP F/W
===========================================================================
